timing analysis的意思

timing analysis中文翻譯：

[計]定時分析

相似詞語短語

analysis───n.分析；分解；驗定

timing differences───時間性差異

statement analysis───n.財務報表分析；財務報表分析；決算表分析

forenoon timing───上午時間

timing chain───[儀]定時鏈

wronging timing───錯誤的時間

conjoint analysis───聯合分析；組合分析；結合分析

timing diagram───計時圖；時間圖；正時圖，定時圖

valve timing───[機]氣門正時；[機]閥定時

雙語使用場景

A tool for timing analysis of UML sequence diagrams is described in this paper.───文章描述了一個對帶時間約束的UM L序列圖進行分析的工具。

The timing analysis in the design of digital integrated circuits is described.───文章對數字集成電路設計中的時序分析作了一個概要的介紹。

Implementation of static timing analysis.───靜態時序分析的實現。

Understanding of the concept of timing. Able to perform static timing analysis.───具備時序概念，能進行靜態時序分析。

A new statistical model of gate delay and a new statistical static timing analysis method are proposed.───提出了一種新的門單元延遲的統計分析模型和一種新的統計靜態時序分析方法。

familiar with ic developing environments including logic synthesis, timing analysis and verilog simulation.───熟悉邏輯綜合，時序分析，verilog仿真等ic開發環境。

Experience with Industry standard design tools for RTL synthesis and timing analysis required.───經驗和行業標準設計，工具和時序分析需要RTL合成。

Based on the layout static timing analysis, the clock period was optimized by the clock skew scheduling utilizing the DCCB.───利用此特性，基于電路版圖時序分析，通過重構DCCB單元進行時鐘偏差調整，優化時鐘周期。

Delay look-up table(LUT) of standard logic circuits are useful in applications such as auto - synthesis and static timing analysis.───門電路延時參數的查找表在電路邏輯綜合及靜態時序分析中均有重要應用。

英語使用場景

The verification includes RTL simulation, gate level simulation and static timing analysis.

Wire wrap large white pearls with BRIGHT silver wire. Please make timing analysis as your work them.

The article presents some concepts of the post route timing analysis in HDL design and then introduces the usage of the Static Timing Analysis tool TIMING ANALYZER of MAXPLUSII.

Based on the layout static timing analysis, the clock period was optimized by the clock skew scheduling utilizing the DCCB.

We also triad to apply the new timing analysis method to X - ray binaries.

Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed.