transfer level的意思

transfer level中文翻譯：

傳輸級別

相似詞語短語

transfer───v.轉讓；轉接；移交；轉移（地方）；（使）換乘；轉存，轉錄；調動（工作）；傳染，傳播；使（運動員）轉隊；把（錢）轉到另一賬戶，機構上；n.（地點的）轉移；（工作的）調動；已調動的人或東西；權力的移交；運動員轉會；（公共汽車、飛機等的）轉移；（財產的）轉讓；數據的拷貝；圖畫，圖案；轉車票

level───n.水平；標準；水平面；vt.使同等；對準；弄平；adj.水平的；平坦的；同高的；n.(Level)人名；(法)勒韋爾；vi.瞄準；拉平；變得平坦

transfer paper───n.摹寫紙

transfer station───圖像轉移設備；傳送站；傳輸站

mail transfer───信匯，郵匯

transfer case───分動箱，變速箱；分動器，分動箱；變速箱

mouthfuls transfer───口轉移

custody transfer───運輸監護；密閉輸送

embryo transfer───胚胎移植；胚胎轉移；胚胎植入；胚泡移植

雙語使用場景

main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).───行為級綜合，其基本任務是完成數字系統行為描述到寄存器傳輸級（RTL）描述的轉換。

The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.───寄存器傳輸級（RTL）描述是目前應用最廣泛的電路設計描述形式。

Generally the higher quality of labor force, the transfer speed is faster than the lower quality of labor, while the transfer level is higher.───一般勞動力素質高者，轉移速度要快于勞動力素質低者，同時轉移層次也較高。

We base on it to establish abstract model between the sequential executable codes and the register transfer level (RTL) description.───我們依該方法在循序可執行程式碼和暫存器傳輸層級間建立抽象模型。

Most CAD tools allow IP verification to be performed by simulating the IP cores at register transfer level (RTL) or at the gate level [4].───多數CAD工具允許IP證明由模仿進行IP核心在記數器調動水平（RTL）或在門水平[4]。

High Level Synthesis Method for Clustered Register Transfer Level Architecture───面向分模塊寄存器傳輸級結構的高層次綜合方法

The construction process control of high level building structure transfer-level───高層建筑結構轉換層施工過程控制

machines should be installed after the transfer level;───用戶注意事項：1，機器安裝后應調水平；

英語使用場景

And the process of functional verification consists of the implementation of RTL (register transfer level) simulation, gate level simulation and post-layout simulation in the process of design.

The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).

The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.

In VLSI design, gate level fault simulation is often too slow to meet the demand of time- to-market. Thus the register transfer level (RTL) fault simulation has become a hot topic recently.

We base on it to establish abstract model between the sequential executable codes and the register transfer level (RTL) description.

RTL(register transfer level) functional verification system for package assembly function in IPOA application is illustrated in this paper.

The influence of architectures on synthesis methods is discussed, and a clustered register transfer level architecture as object architecture is presented.

The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.

This thesis has accomplished the design of register transfer level (RTL) of every unit in the digital processing module, and passed function verification, logic synthesis, and gate level verification.