chip level的意思

chip level中文翻譯：

片級

相似詞語短語

crisper chip───脆片

chip shot───打高球；近穴擊球；削球；n.[體]近穴擊球

potato chip───n.炸土豆片

chip dale───奇普戴爾

chip ingram───芯片ingram

chip gaines───奇普·蓋恩斯

said chip───奇普說

computer chip───電腦芯片

level───n.水平；標準；水平面；vt.使同等；對準；弄平；adj.水平的；平坦的；同高的；n.(Level)人名；(法)勒韋爾；vi.瞄準；拉平；變得平坦

雙語使用場景

loosely-coupled architecture being scaled down to the chip level.───其看作松耦合架構按比例縮小至芯片級。

They can be classified into wafer level, chip level, and package level stacking.───它們可以分為圓片級封裝、芯片級封裝、和封裝面。

We clearly demonstrated that we can do it at the unit chip level," says Kim.───金說“我們證實了我們可以在單元芯片級做到這個。”

The deployment comes a year after ETH and IBM scientists announced plans to collaborate on chip-level water-cooling and energy reuse.───這項研究于1年前開始，當時ETH和IBM的科學家宣布他們計劃合作研究芯片級水冷及能源循環利用的項目。

The advantages of this chip-level spring damping structure are one integrated, good consistency and engineering applications.───該芯片級彈簧減震結構具有一次集成、一致性好、易于組陣、工程應用方便等特點。

Today, chip-level multiprocessing provides more CPUs on a single chip, permitting even greater performance due to reduced memory latency.───現在，芯片級多處理能夠在單個芯片上提供更多的CPU，由于減少了內存延遲，因而可獲得更高的性能。

This paper mainly discusses on the evolving three - dimensional integration technology of silicon - based chip - level electronics.───本文圍繞目前電子封裝業正在興起的硅基芯片級三維集成技術展開論述。

Tightly-coupled multiprocessing refers to chip-level multiprocessing (CMP).───緊密耦合多處理指芯片級多處理（CMP）。

Performs block level and full chip level simulations using logic and mixed-signal simulators.───按照邏輯和混合信號仿真原則進行模塊和芯片級的仿真。

英語使用場景

Module level micro architecture design and RTL implementation. Chip level integration.

With the support of advanced EDA tools and chip level verification environment, in this paper, the code coverage analysis and statistic job for NSR module are also done.

It can satisfy the requirement of digital plugboard test and carry out the plugboards test to chip level. Thus it has wide application potential.

In the LED chip level, how to maintain the internal quantum efficiency under high current injection is a big challenge for the material engineering.

They can be classified into wafer level, chip level, and package level stacking.

Think about the loosely-coupled architecture being scaled down to the chip level.