clock line的意思

clock line中文翻譯：

時鐘線

相似詞語短語

clock───vt.記錄；記時；n.(Clock)人名；(英)克洛克；n.時鐘；計時器；vi.打卡；記錄時間

line line───線條線條

twelveo clock───十二點鐘

electric clock───[儀]電鐘

pelvic clock───骨盆時鐘

o clock───n.點鐘

speaking clock───n.電話報時服務

sextant clock───六分儀鐘

gpu clock───gpu時鐘

雙語使用場景

The host changes the data line only when the Clock line is low, and data is read by the device when Clock is high.───只有當時鐘線為低的時候，主機才可以改變數據線(也就是將數據寫入到數據線)。數據將在時鐘為高電平的時候被設備讀齲。

The host has ultimate control over the bus and may inhibit communication at any time by pulling the Clock line low.───主機對總線有最高的控制權，在任何時候通過將時鐘線拉低就可以禁止通信。

In a preferred embodiment, this estimation is made by identifying a best clock line between the first and second convex hulls.───在優選實施例中，通過識別第一和第二凸包之間的最佳時鐘線來進行此估計。

The system raises the 'clock' line to allow the next transmission.───系統拉高時鐘將允許下一次傳輸。

If the device finds the system holding the 'clock' line inactive, the transmission is terminated.───如果設備發現主機系統將電平拉低，就終止傳輸。

The auxiliary device checks the 'clock' line. If the line is inactive, output from the device is not allowed.───輔助設備（指鍵盤）檢查時鐘線，如果時低電平，禁止發送數據。

The auxiliary device checks the 'clock' line during the transmission at intervals not exceeding 100 microseconds.───設備在傳輸過程中檢查時鐘線間隔不超過100us。

英語使用場景

When the keyboard or mouse wants to send information, it first checks the Clock line to make sure it's at a high logic level.

Results indicate that when fault duration is shorter than phase difference of three clocks, enhanced ST-TMR can almost mask the SEU in combinational logic circuit and clock line.