digital delay的意思

digital delay中文翻譯：

數字式延遲

相似詞語短語

delay───v.延期；（使）耽擱；推遲；n.延遲的時間；延期；延時；延遲器；n.(Delay)（美）德萊（人名）

digital───n.數字；鍵；adj.數字的；手指的

appreciable delay───明顯延遲

irritating delay───刺激性延遲

flight delay───航班延誤

time delay───時間延遲; 時延; 延時; 落后；延時，延遲

delay time───[電子]延遲時間，推遲時間；延遲時間，滯后時間，緩發時間; 時延

delay to───延遲到

ambidexterity delay───雙靈巧延遲

雙語使用場景

Based on digital delay-locked loop, the mix signal technique is used to implement the digital delay locked loop with the resource control technique.───以數字延遲鎖相環為基礎，并采用數模混合技術，實現了帶電源控制的數字延遲鎖相環。

In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.───在電路設計過程中，對后級接口電路進行了最優化設計，采用VHDL描述的方式實現了低壓數字延時電路模塊的設計。

RN1406 Pinout: RCDs digital delay lines have been designed to provide precise tap delays with all the necessary drive and pick-off circuitry.───RN1406引腳說明：剛果民盟數字延遲線的設計提供所有必要的驅動器精確自來水延誤和挑選過的電路。

By the digital delay-locked loop (DLL) the timing precision of the display interface was improved.───利用數字延遲鎖相環邏輯，提高了顯示接口時序控制精度。

Digital Delay Compensates for Differences in Link Paths.───為不同鏈接路徑提供數字延時補償。

Finally, the MP3 decode frequency equalizer and some digital delay effects are implemented on SM350 platform.───最后在SM350平臺上實現了MP3解碼的頻域均衡器和數字延時音效。

Digital Delay Technique and its Practice for Broadcast Signal───廣播信號數字延時技術與實踐

Design and realization of nanosecond digital delay and pulse generator───納秒延時同步脈沖產生器的設計與實現

The Research of Digital Delay Signal Integrity in Laser Targeting───激光打靶數字延時信號完整性的研究

英語使用場景

RN1406 Pinout: RCDs digital delay lines have been designed to provide precise tap delays with all the necessary drive and pick-off circuitry.

Based on digital delay-locked loop, the mix signal technique is used to implement the digital delay locked loop with the resource control technique.

The best one is a digitally produced effect using a digital delay line having at least 16-bit resolution.

In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.

This paper proposes a new gate drive method for active clamped quasi resonant converters. Instead of a digital delay circuit, only a resistor and a diode are added to produce correct drive waveforms.