青年中文gate level的意思
gate level中文翻譯：
門水平
gate───vt.給…裝大門；n.(Gate)人名；(英)蓋特；(法、瑞典)加特；n.大門；出入口；門道
level───n.水平；標準；水平面；vt.使同等；對準；弄平；adj.水平的；平坦的；同高的；n.(Level)人名；(法)勒韋爾；vi.瞄準；拉平；變得平坦
gate chalk───門粉筆
la gate───拉門
arrival gate───到達口；下機門
festinate gate───festinate門
cow gate───在公地上放牧一頭牛的權利
pearly gate───珍珠門
colline gate───柯林斯門
Using gate level modeling might not be a good idea for any level of logic design.───使用門級建模對于任何邏輯設計都不是一個好的設計。
Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping.───高級綜合結果中常量元件和輸出懸空端口導致門級工藝映射結果中存在顯式冗余。
energy optimization methods in circuit level and gate level have been investigated widely.───線路層、門層等低層能量優化方法已經得到廣泛研究。
Most CAD tools allow IP verification to be performed by simulating the IP cores at register transfer level (RTL) or at the gate level [4].───多數CAD工具允許IP證明由模仿進行IP核心在記數器調動水平（RTL）或在門水平[4]。
each student completes a gate-level design for a RISC processor during the semester.───每一位學生必需在本學期完成一個邏輯閘級的簡單指令集計算機（RISC）處理器設計。
All of these bring the challenge to the traditional gate-level test.───這些現狀都帶來了對傳統門級測試的挑戰，發展高層測試迫在眉睫。
Combined Novel Gate Level Model and Critical Primary Input Sharing for Genetic Algorithm Based Maximum Power Supply Noise Estimation───基于最大電源噪聲門級模型的遺傳算法電源噪聲估計
Multi-objective Adaptive Genetic Algorithm for Gate-Level Evolution of Logic Circuits───基于多目標自適應遺傳算法的邏輯電路門級進化方法
Optimization of Explicit Redundancy in Gate-Level Technology Mapping───門級工藝映射中顯式冗余的優化
The verification includes RTL simulation, gate level simulation and static timing analysis.
And the process of functional verification consists of the implementation of RTL (register transfer level) simulation, gate level simulation and post-layout simulation in the process of design.
This thesis has accomplished the design of register transfer level (RTL) of every unit in the digital processing module, and passed function verification, logic synthesis, and gate level verification.
In VLSI design, gate level fault simulation is often too slow to meet the demand of time- to-market. Thus the register transfer level (RTL) fault simulation has become a hot topic recently.
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.