bit line的意思

bit line中文翻譯：

[電子]位線

相似詞語短語

bit───adj.很小的；微不足道的；n.[計]比特（二進位制信息單位）；少量；馬嚼子；輔幣；老一套；一點，一塊；adv.有點兒；相當；vt.咬（bite的過去式和過去分詞）；vt.控制

bit by bit───一點兒一點兒地，逐漸地; 點點滴滴; 一點一滴；一點一點地

line line───線條線條

bit backup───位備份

bit into───咬進；啃

fillister bit───凹形鉆頭

df bit───測向鉆頭

casing bit───套管鉆頭

line───n.(Line)人名；(英)萊恩；(俄)利涅；vt.排成一行；劃線于；以線條標示；使…起皺紋；vi.排隊；站成一排；n.路線，航線；排；繩

雙語使用場景

contact plug is electrically connected to the common doped region and the bit line is disposed over the substrate.───接觸窗插塞電性連接至共用摻雜區域，且位線配置于基底上。

The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines.───該半導體存儲器件包含連接到一對位線的位線感測放大器。

Moreover, the resistive memory element is connected between the contact plug and the bit line.───此外，電阻式存儲器元件連接于接觸窗插塞與位線之間。

A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells.───位于絕緣層上的位線電連接到多個電阻存儲器單元中的最后一個。

A first global bit line may be connected to a first one of the plurality of transistors.───與所述多個晶體管中的第一晶體管相連的第一全局位線；

The top electrode 15 itself can be used to constitute a bit line, or a separate bit line can be provided.───上電極15自身可以用來構成位線，或者可以設置獨立的位線。

The SRAM memory means comprises a first pass-gate FET (T6) which is coupled between a first node (A) and a bit line-bar (BLB).───SRAM存儲器裝置包括耦合在第一節點（A）和位線條（BLB）之間的第一門FET（T6）。

The contact plug is electrically connected to the common doped region and the bit line is disposed over the substrate.───接觸窗插塞電性連接至共用摻雜區域，且位線配置于基底上。

英語使用場景

Moreover, the resistive memory element is connected between the contact plug and the bit line.

The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines.

In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation.

The resistive memory cell comprises a first gate, a second gate, a common doped region, a contact plug, a bit line and a resistive memory element.

The state of the memory element can thereby be detected by a voltage comparator sense amplifier that is connected to the bit line.

The reset state of a bit line is canceled when selected and connected to a read circuit for read, and information stored in a selected memory cell is read via the selected bit line.

This ensures that during read determination operation in the next read cycle, the potential of a selected bit line will not vary with the bit line residual discharge in the previous read cycle.

A memory device having an off-current (Ioff) robust precharge control circuit and a bit line precharge method are provided.