sequential logic的意思

sequential logic中文翻譯：

[計]時序邏輯；順序邏輯；循序邏輯

相似詞語短語

logic───n.邏輯；邏輯學；邏輯性

cartesian logic───笛卡爾邏輯

effectual logic───有效邏輯

sophism logic───詭辯邏輯

swirl logic───漩渦邏輯

circ logic───電路邏輯

logic puzzles───邏輯猜謎

chop logic───v.強詞奪理；咬文嚼字；強詞奪理；爭辯

logic bomb───邏輯炸彈（程序）；[計]邏輯炸彈

雙語使用場景

Sequential logic synthesis is an important part of RTL synthesis system design.───時序邏輯綜合是RTL綜合系統設計中的一個重要部分。

This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.───本實驗指導書分為兩大部分：組合邏輯，時序邏輯。

The second is where you have to integrate the loop closely with the sequential logic.───第二點是，人們必須將一些控制環與順序邏輯控制更緊密地集成。

The race and hazard in the sequential logic circuit is quite essential and must be considered when designing logic circuit.───時序邏輯電路中的競爭冒險是電路設計中必須考慮到的重要方面。

This system uses the main techniques are: sequential logic circuit technology.───此系統使用的主要技術是：時序邏輯電路技術。

This method which is called tendency value table is applied to some sequential logic circuits.───本文還分析了開關對邏輯電路產生干擾的原因和抑制方法。

a complete line of equipment sintering automatic sequential logic process cycle time is not more than 95 seconds.───在線工藝設備完成一個燒結自動循環循序邏輯流程時間不大于95秒。

It is a sequential logic circuit; its outputs depend not only on the current input values, but also on how they have changed in the past.───這是一種時序電路，它的輸出不僅依賴于當前的輸入值，還與以前輸入值是如何變化的有關。

英語使用場景

In the design of the sequential logic circuit, redundant state is used to assign the state, so the assignment is more consistent to the A -H rule, and simple sequential structure can be obtained.

The method modifies the normal sequential logic by adding additional shift function module to improve the controllability and the observability.

Sequential logic synthesis is an important part of RTL synthesis system design.

In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.

This paper presents a multiple fault test simulator for sequential logic circuit. The simulator is implemented in serial-parallel to save memory.

Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.

Flip - flops are a key component and memory cells of sequential logic circuit.